The present invention relates to a method of testing pulse delay times in circuits to be checked, especially semiconductor integrated circuits (hereinafter referred to as ICs).
In a recent IC technology, the increasing degree of integration has been demanded with a large number of pins and high operation speed required. When any defect is located in such highly integrated ICs after the mounting thereof on a system, it is very difficult to detect one of the ICs having a certain fault and the kind of that fault. Accordingly, a sufficient test is required in the state of a single IC in order to improve a yield in the succeeding steps.
Test modes for a single IC include a function test, a DC test and an AC test. In the function test, the logical function of IC is checked. In the DC test, the source current, input leakage current, output voltage and output current of IC are checked in order to determine whether they fall within standards or not. The AC test measures a delay time in IC, i.e. a time from an instant at which an input pulse is applied to an input pin of the IC to an instant at which an output pulse is delivered at an output pin thereof.
Among these test modes, the AC test has a problem resulting from the increased integration and operation speed of IC. When one IC consists of only logical gates such as AND gates or OR gates or consists of only flip-flops, the AC test encounters no special problem. With the increased integration of IC, however, an IC has been developed which incorporates the combination of gates and flip-flops, especially two or more stages of flip-flops. For such an IC, the mere application of an input pulse does not sometimes result in the delivery of an output. Namely, a status setting is required to the associated flip-flop when the pulse passes through the IC. Thus, the status setting is required for the measurement of a pulse delay time in IC and any entrance of noises into an input signal pin is not acceptable during a period from the status setting to the completion of delay time measurement. If noises enter the input signal pin, the value of the set status may change. Similarly, when after a first test of delay time measurement for a certain path a second test is desired for another path, the entrance of noises into the input signal pin must be avoided in order to save a test time and a status setting time while keeping the previous status setting.
An input pin of a circuit to be checked is connected through switching elements with an input driver which delivers a predetermined level of voltage for the status setting and with a pulse generator which generates pulses. The switching element may be an electronic switch such as a transistor or a relay. However, in the case where the transistor is used, its characteristic and performance must be carefully selected and a highly accurate test is impossible because of its action of deteriorating the pulses from the pulse generator or making the sharpness of the pulse waveforms weak. These problems may be eliminated in the case where the relay is used as the switching element. A test system using relays as the switching elements is known in "S157 PULSE PARAMETER TEST SYSTEM Maintenance Manual" pp. 9.1.1-9.2.3 published by TERADYNE, Inc. However, even when the relays are used as the switching elements, the entrance of noises may not be avoided depending upon the opening-closing sequence of the relays.